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RF128x32
- 基于verilog的128*32RAM设计代码-The RAM-based design code verilog
ram_test
- 基于Verilog的存储器模块及其测试模块-a ram module based on Verilog HDL
ddr3_uniphy_siv_example_restored
- A system that is written in Verilog to be able to read and write data to a DDR3 RAM by Altera FPGA
syncram
- verilog rtl and testbench code for single port sync ram
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
RAM-verilog
- 非常 好的资料，希望大家都能喜欢， 谢谢大家的支持-Very, very good information, I hope people will like it, thank you for your support
ahb_slave_ssrw
- 通过AHB总线简单访问register/RAM 的verilog 子模块 ssrw stands for simple single read write.- submodule used for simple configuration register/RAM accesses ssrw stands for simple single read write.
RAM_InterWave
- RAM 通过ip核的生成使用verilog 的编写的，可以拿来直接进行例化使用。-RAM generated by using verilog ip core prepared, can be used directly instantiated using.
sindeshengcheng
- 正选函数的产生，由ram生成地址 verilog编写-Being elected function generates an address verilog written by ram
RAM_basic
- RAM Implementation using Verilog Codes
SPI_ram
- verilog读写RAM的程序 verilog读写RAM的程序-this is a program of that reading or writting a ram.
rs232_des
- uart verilog code using ram and a-uart verilog code using ram and all
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
video_center_scan_scaler_alpha_blend
- 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discr iption
SDRAM_interface
- SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a re
ram_3
- RAM的verilog描述，包含向量名定义，顶层设计等等的精确描述-RAM in verilog descr iption, including vector name is defined, an accurate descr iption of the top-level design, etc.
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
sp6ex18
- 基于Verilog HDL的对片内RAM进行连续读写测试实例-Based on the on-chip RAM for continuous reading and writing test cases for Verilog HDL
gds8k_32bit_1M
- 一款SRAM的verilog代码及版图信息-verilog codes and layout information of a RAM
IIC
- Verilog IIC程序，RAM接口，方便调试，一主多从-Verilog IIC program, RAM interface, easy to debug, and more a master